1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device with a Fin Field Effect Transistor (FinFET) and a method of fabricating the same.
2. Description of the Related Art
Integration density of semiconductor devices continues to increase in order to improve performance and to reduce manufacturing costs. In order to increase the integration density, techniques that reduce a feature sizes of semiconductor devices are required. When fabricating contemporary semiconductor devices, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been shortened to enhance the integration density and speed of semiconductor devices. However, the shortened channel length results in short channel effects that degrade active switch characteristics of the device. Moreover, because of being a planar channel device where channels are formed to be parallel with a surface of a semiconductor substrate, the MOSFET is not only unfavorable for device size reduction but also is not conducive to preventing short channel effects.
Recently introduced FinFET devices have a tri-gate structure in which a fin-shaped three-dimensional active region is formed, and a gate electrode encircles both side surfaces and an upper surface of the fin, thereby forming a channel with a three-dimensional structure instead of a planar structure. The tri-gate structure has a channel perpendicular to a surface of a substrate to increase the effective channel width, which is different from the planar MOSFET. Therefore, the short channel effects are mitigated in FINFET devices relative to the short channel effects of MOSFET devices. FinFET devices are disclosed in, e.g., U.S. Pat. Nos. 6,391,782 and 6,664,582, the disclosures of which are incorporated herein by reference.
As FinFET devices continue to become increasingly integrated, they too experience short channel effects. Accordingly, efforts to reduce the short channel effects are conducted by changing the doping profile of a channel region in the FinFET as in the MOSFET (referred to as “local channel ion implantation”). However, the conventional local channel ion implantation approach has a disadvantage in that both the source and the drain regions are doped as well as the channel region.
When an n-type FinFET is used as an example, the channel region is doped with a p-type impurity via local channel ion implantation. In this case, the p-type impurity is doped into a substrate to form a p-type ion implantation region. If the n-type source and drain are formed in a subsequent process, bottom surfaces of the n-type source and drain contact the p-type ion implantation region in which a source and a drain are formed. If the regions with mutually opposite conductivities meet to form a junction, the junction leakage current of the device can increase. Therefore, a drawback of the conventional local channel ion implantation method is that off-leakage current of the resulting device can be increased.